As is well known in the art, digital and linear functions are often performed by integrated circuits using either bipolar or metal-oxide-semiconductor (MOS) technology. Bipolar integrated circuits, of course, provide higher speed operation and greater drive currents than the MOS circuits, at the cost of higher power dissipation, especially when compared against complementary MOS (CMOS) circuits. Recent advantages in manufacturing technology have allowed the use of both bipolar and CMOS transistors in the same integrated circuit (commonly referred to as BiCMOS devices). Examples of BiCMOS structures and methods for making the same are described in copending application Ser. No. 008,910, filed Jan. 30, 1987, now abandoned, and applications Ser. No. 129,261 filed Dec. 7, 1987, now abandoned, and Ser. No. 366,224 filed Jun. 12, 1989 now U.S. Pat. No. 4,958,213 which is a continuation of application Ser. No. 129,271 filed Dec. 7, 1987 (now abandoned), all assigned to Texas Instruments Incorporated.
The formation of BiCMOS devices may of course be accomplished by forming the bipolar transistors according to known techniques in selected areas of the device, by forming the MOS transistors according to known techniques in selected areas of the device, and interconnecting the two types of transistors. However, certain features of each type of transistor tend to be incompatible, from a process standpoint, with the other type, requiring a large number of process steps to form each. It is therefore preferable in the manufacture of such BiCMOS circuits to utilize structures which are useful in both types of transistors, in order to minimize the process complexity and cost. Such dual utilization of structural components and process steps, however, generally results in a process which is less than optimal for either the bipolar or the MOS transistors, or both.
Prior methods for forming the bipolar transistors in such structures, such as described in said application Ser. No. 008,910, have incorporated thin oxide layers between the diffused base region and the overlying emitter electrode (generally formed of polysilicon). The thin oxide over the base is generally formed in the same step as the gate oxide for the MOS transistors, and therefore is generally of a thickness on the order of 20 nm.
Such thin oxides separating the base region from the emitter electrode cause certain problems, however. Firstly, performance of the bipolar transistors degrades as the emitter-to-base capacitance increases. Of course, such capacitance increases as the dielectric thickness therebetween decreases, making it preferable to have a thicker dielectric between the emitter and the base region. In addition, a thin dielectric between the emitter electrode and the base region is inherently weaker to stress from subsequent processing steps such as contact etch, silicidation, and metal deposition and sinter. Furthermore, a thin dielectric also increases the risk that a contact via formed over the oxide for connecting an overlying metallization layer to the emitter electrode will leak to the base region. This can occur in the event that the contact via is overetched through the emitter electrode, in which case the dielectric under the emitter electrode will be further thinned, in turn further increasing the emitter-to-base capacitance. In extreme cases, the dielectric may be etched completely through, shorting the overlying metal and the emitter electrode to the base region.
The method described in the above-referenced application Ser. No. 008,910, using the thin MOS gate oxide thin dielectric over the base region, avoids the stress and overetch problems by making contact to the polysilicon emitter electrode at a location away from the contact to the base region. Such a configuration does not address the emitter-to-base capacitance problem, and adds the disadvantage of increasing the emitter resistance.
The method described in said copending application Ser. No. 366,224, now U.S. Pat. No. 4,958,213, describes the formation of a bipolar transistor in a BiCMOS process where the same polysilicon layer is used to form the emitter and gate electrodes, but where a thicker base oxide is provided under the emitter electrode than under the gate electrodes. This is accomplished by placing a material which inhibits oxidation, such as silicon nitride, over the regions where the MOS transistors are to be formed but not over the base region. A thermal oxide is then formed over the base region to the desired thickness, and the intrinsic base region implant is performed with the nitride over the non-base regions masking the implant thereat. The nitride oxidation mask is removed from the MOS regions, and a contact is etched through the base oxide for the emitter contact. The structure is completed by deposition of polysilicon, followed by conventional source/drain and extrinsic base implant and diffusion steps.
This method of application Ser. No. 366,224 is effective to form an oxide layer under the emitter electrode which is thicker than the gate oxide of the MOS transistors, and which therefore provides for reduced emitter-base capacitance and allows emitter contacts to be nested within the base region. It is desirable, however, to improve a number of facets of this process. Firstly, it is desirable to reduce high temperature processing after dopant has been implanted for formation of the base region, in order to maintain minimal depth of diffused regions as the size of the structures are scaled to smaller geometries. Secondly, it is desirable to control the thickness of the oxide over the base region independently from other structures on the surface of the wafer, such as diffused regions. Thirdly, it is desirable to simplify the process for forming the bipolar transistor in a BiCMOS structure. Fourthly, it is desirable to allow for the scaling of the emitter contact through the base oxide in a manner which does not depend upon lithographically defining the contact opening.
It is therefore an object of this invention to provide a process for forming a BiCMOS structure which incorporates a deposited dielectric layer between the base and emitter of the bipolar transistors in conjunction with a thermal oxide under the gate of the MOS devices.
It is yet another object of this invention to provide such a process which provides such a thicker dielectric with reduced thermal processing after the formation of the intrinsic base region.
It is yet another object of this invention to provide such a process which provides for independent control of the base oxide relative to other structures such as diffusion depths.
It is yet another object of this invention to provide such a process which is relatively simple in the number of processing steps.
It is yet another object of this invention to provide such a method where the emitter contact can be non-lithographically defined so that the structure can be scaled to smaller physical dimensions.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.